A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs

被引：20

作者：

Fazan, PC ^{[1
]}

Okhonin, S ^{[1
]}

Nagoga, M ^{[1
]}

Sallese, JM ^{[1
]}

机构：

[1] Innovat Silicon Solut, CH-2525 Le Landeron, Switzerland

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012775

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new compact memory architecture is proposed for embedded Dynamic Random Access Memory (eDRAM) cells. By exploiting the floating body effect of partially depleted Silicon On Insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.

引用

页码：99 / 102

页数：4

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