Multithreaded processors

被引:23
作者
Ungerer, T [1 ]
Robic, B
Silc, J
机构
[1] Univ Augsburg, Dept Comp Sci, Augsburg, Germany
[2] Univ Ljubljana, Fac Comp & Informat Sci, Ljubljana, Slovenia
[3] Jozef Stefan Inst, Comp Syst Dept, Ljubljana, Slovenia
关键词
D O I
10.1093/comjnl/45.3.320
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors. One solution is the additional utilization of more coarse-grained parallelism. The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance. The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip. In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline. Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor. The execution units are multiplexed between the threads in the register sets. Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple threads each cycle. Simultaneous multithreaded processors combine the multithreading technique with a wide-issue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from different threads simultaneously. This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.
引用
收藏
页码:320 / 348
页数:29
相关论文
共 132 条
[1]   SPARCLE - AN EVOLUTIONARY PROCESSOR DESIGN FOR LARGE-SCALE MULTIPROCESSORS [J].
AGARWAL, A ;
KUBIATOWICZ, J ;
KRANZ, D ;
LIM, BH ;
YEUNG, D ;
DSOUZA, G ;
PARKIN, M .
IEEE MICRO, 1993, 13 (03) :48-61
[2]  
AGARWAL A, 1995, ACM COMP AR, P2, DOI 10.1109/ISCA.1995.524544
[3]   A dynamic multithreading processor [J].
Akkary, H ;
Driscoll, MA .
31ST ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 1998, :226-236
[4]   Blue Gene: A vision for protein science using a petaflop supercomputer [J].
Allen, F ;
Almasi, G ;
Andreoni, W ;
Beece, D ;
Berne, BJ ;
Bright, A ;
Brunheroto, J ;
Cascaval, C ;
Castanos, J ;
Coteus, P ;
Crumley, P ;
Curioni, A ;
Denneau, M ;
Donath, W ;
Eleftheriou, M ;
Fitch, B ;
Fleischer, B ;
Georgiou, CJ ;
Germain, R ;
Giampapa, M ;
Gresh, D ;
Gupta, M ;
Haring, R ;
Ho, H ;
Hochschild, P ;
Hummel, S ;
Jonas, T ;
Lieber, D ;
Martyna, G ;
Maturu, K ;
Moreira, J ;
Newns, D ;
Newton, M ;
Philhower, R ;
Picunko, T ;
Pitera, J ;
Pitman, M ;
Rand, R ;
Royyuru, A ;
Salapura, V ;
Sanomiya, A ;
Shah, R ;
Sham, Y ;
Singh, S ;
Snir, M ;
Suits, F ;
Swetz, R ;
Swope, WC ;
Vishnumurthy, N ;
Ward, TJC .
IBM SYSTEMS JOURNAL, 2001, 40 (02) :310-327
[5]  
ALVERSON G, 1995, LECT NOTES COMPUTER, V949, P19
[6]   Tera computer system [J].
Alverson, Robert ;
Callahan, David ;
Cummings, Daniel ;
Koblenz, Brian ;
Porterfield, Allan ;
Smith, Burton .
Conference Proceedings - International Conference on Supercomputing, 1990,
[7]  
[Anonymous], 1999, PROCESSOR ARCHITECTU
[8]  
[Anonymous], 1997, COMPUTER
[9]  
BACH P, 1997, P 30 HAW INT S SYS S
[10]   Memory system characterization of commercial workloads [J].
Barroso, LA ;
Gharachorloo, K ;
Bugnion, E .
25TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 1998, :3-14