Test Pattern Generation Technology Based on TPAC and LFSR

被引：0

作者：

Guo, M. -M. ^{[1
]}

Kuang, J. -Sh ^{[1
]}

机构：

[1] Hunan Univ, Sch Informat Sci & Engn, Changsha, Hunan, Peoples R China

来源：

2011 AASRI CONFERENCE ON ARTIFICIAL INTELLIGENCE AND INDUSTRY APPLICATION (AASRI-AIIA 2011), VOL 2 | 2011年

关键词：

IC Testing; Test Patterns Generation; Fault Efficiency; Self-Feedback Test; LFSR;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Linear feedback shift register (LFSR) is widely used in pseudo random test pattern generator, taking advantage of simple structure, little hardware cost, being easy to control and realize. Test patterns applied by circuit under test (TPAC) is a novel self -test technology, which regards the circuit under test as available resource, but uses many multiplexes. This paper drawn on the experience of TPAC and realized a new circuit self test technology based on LFSR. The experiment results on the ISCAS'85 benchmark circuits show that the proposed scheme can reduce the extra area effectively.

引用

页码：257 / 260

页数：4

共 5 条

[1]

[Anonymous], IEEE WORKSH DDECS

[2]

Jin Liyun, 2010, RES BIST SCHEME TEST, P41

[3] On identifying don't care inputs of test patterns for combinational circuits [J].

Kajihara, S ;

Miyase, K .

ICCAD 2001: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2001, :364-369

[4] A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself [J].

Kuang, Jishun ;

Ouyang, Xiong ;

You, Zhiqiang .

PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, :75-+

[5]

Yang Jing, 2010, STUDY INCREASING LEN, P31

← 1 →