Area-Conscious Reconfigurable Arithmetic Unit Architecture for High-Performance DSP

Reconfigurable architecture requires many processing elements and a configuration switches for reconfigurable module. The structure consumes significant amount of area. Area reduction is necessary for the reconfigurable architecture to be used as a competitive IP core in embedded systems. In this paper, we propose an area-conscious reconfigurable arithmetic unit architecture for high-performance DSP that efficiently reduces area consumption without performance degradation. The results show that proposed architecture saves up to 57.97% of the total area consumed in reconfigurable arithmetic unit with reduced its size compared to previous architecture.