A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

被引:72
作者
Hu, Jason [1 ]
Dolev, Noam [1 ]
Murmann, Boris [1 ]
机构
[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
关键词
CMOS; dynamic amplifier; offset calibration; pipelined ADC; source follower; switched-capacitor circuits; TO-DIGITAL CONVERTER; CMOS; NOISE; 10-BIT;
D O I
10.1109/JSSC.2009.2014705
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A low-power pipelined ADC featuring dynamic source follower amplifiers is presented in this paper. The proposed dynamic source follower-based architecture provides a low-power alternative to the traditional opamp-based MDAC circuits. This new type of circuit dynamically charges its load capacitance without a large bias current, leading to significant power savings. The presented ADC includes a low-power comparator with offset calibration and uses digital calibration for gain correction. Measured results indicate that the 9.4-bit, 50-MS/s prototype ADC achieves an SNDR of 49.2 dB (7.9 ENOB) and consumes 1.44 mW from a 1.2-V supply, resulting in a figure of merit of 119 fJ/conversion-step. The converter's input capacitance is 90 fF and the total active area is 0.123 mm(2) in a 90 nm CMOS process.
引用
收藏
页码:1057 / 1066
页数:10
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