Adaptive Run-length Encoding Circuit Based on Cascaded Structure for Target Region Data Extraction of Remote Sensing Image

In order to reduce the pressure of data storage and transmission on satellite, researchers implemented a method of object region data extraction from remote sensing image in orbit. This method stores and downloads pixels of interesting region through interesting region labeling. But encoding data volume (EDV), hardware scale and real-time property (RTP) are difficult to be balanced. To solve this problem, the paper proposes the Adaptive Run-length Encoding (ARLE) circuit which is used in target region labeling and applied in FPGA. The circuits are designed upon cascaded structure which is simple, lightweight, modular, extensible and transplantable. Experiment shows that comparing with the existing methods, ARLE circuit has better compression effect and better utilization of resource. And it does not only ensure RTP but also narrow the circuit scale (CS). The target region extraction method can be easily extended to various application scenarios of rapid target region extraction. The ARLE circuit can be directly applied to real-time dataflow encoding between FPGA and external storage devices.