A low-cost input vector monitoring concurrent BIST Scheme

被引:0
作者
Voyiatzis, I. [1 ]
Efstathiou, C. [1 ]
Sgouropoulou, C. [1 ]
机构
[1] Technol Educ Inst Athens, Athens, Greece
来源
PROCEEDINGS OF THE 2013 IEEE 19TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS) | 2013年
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this work a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respect to the required hardware overhead.
引用
收藏
页码:179 / 180
页数:2
相关论文
共 7 条
[1]  
Abramovici M., 1990, DIGITAL SYSTEMS TEST
[2]  
BRGLEZ F, 1985, INT S CIRC SYST
[3]  
Bui Hung Tien, ASICS 2000 AP ASIC 2, p25
[4]  
Kunzmann Arno B., EURO DAC 92 P C EUR
[5]   Algorithm for the generation of SIC pairs and its implementation in a BIST environment [J].
Voyiatzis, I. ;
Haniotakis, T. ;
Halatsis, C. .
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (05) :427-432
[6]  
Voyiatzis I., 2013, P 2 MED WORKSH MED 2, P61
[7]   An input vector monitoring concurrent BIST architecture based on a precomputed test set [J].
Voyiatzis, Ioannis ;
Paschalis, Antonis ;
Gizopoulos, Dimitris ;
Halatsis, Constantin ;
Makri, Frosso S. ;
Hatzimihail, Miltiadis .
IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (08) :1012-1022