Design for hierarchical two-pattern testability of data paths

被引：0

作者：

Altaf-Ul-Amin, M ^{[1
]}

Ohtake, S ^{[1
]}

Fujiwara, H ^{[1
]}

机构：

[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Ikoma 6300101, Japan

来源：

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 2002年 / E85D卷 / 06期

关键词：

design for testability; delay testing; hierarchical testability; two-pattern testability;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces the concept of hierarchical testability of data paths for delay faults. A definition of hierarchically two-pattern testable (HTPT) data path is developed. Also, a design for testability (DFT) method is presented to augment a data path to become an HTPT one. The DFT method incorporates a graph-based analysis of an HTPT data path and makes use of some graph algorithms. The proposed method can provide similar advantages to the enhanced scan approach at a much lower hardware overhead cost.

引用

页码：975 / 984

页数：10

共 14 条

[1] Design for two-pattern testability of controller-data path circuits
Altaf-Ul-Amin, M
Ohtake, S
Fujiwara, H
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (06) : 1042 - 1050
[2] Multiple scan chain design for two-pattern testing
Polian, I
Becker, B
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (01): : 37 - 48
[3] Multiple Scan Chain Design for Two-Pattern Testing
Ilia Polian
Bernd Becker
Journal of Electronic Testing, 2003, 19 : 37 - 48
[4] Multiple scan chain design for two-pattern testing
Polian, I
Becker, B
19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2001, : 88 - 93
[5] Two-pattern generation based on accumulators with 1's complement adders
Voyiatzis, I.
Efstathiou, C.
IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS, 2006, : 365 - 369
[6] Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
Ghosh, I
Raghunathan, A
Jha, NK
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (09) : 1001 - 1014
[7] A DFT Method for Single-Control Testability of RTL Data Paths for BIST
Toshimitsu Masuzawa
湖南大学学报(自然科学版), 2000, (S2) : 52 - 60
[8] A DFT method for BIST of RTL data paths based on single-control testability
Izutsu, M
Wada, H
Masuzawa, T
Fujiwara, H
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 2003, 86 (02): : 84 - 93
[9] A BIST method based on concurrent single-control testability of RTL data paths
Yamaguchi, K
Wada, H
Masuzawa, T
Fujiwara, H
10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 313 - 318
[10] Hierarchical test generation and design for testability methods for ASPP's and ASIP's
Ghosh, I
Raghunathan, A
Jha, NK
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1999, 18 (03) : 357 - 370

← 1 2 →