A new ALD-TiN/COSi2 contact plug process for reliable and low defect density bit-line integration in sub-quarter micron giga-bit DRAM

被引：0

作者：

Park, SG ^{[1
]}

Kang, SB ^{[1
]}

Choi, GH ^{[1
]}

Chung, UI ^{[1
]}

Moon, JT ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Proc Dev Team 2, Semicond R&D Ctr, Yongin 449711, Kyungki Do, South Korea

来源：

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2002年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports a new ALD-TiN/CoSi2 contact plug process for giga-bit scale DRAM bit-line contacts. Using this technology, we obtained a low contact resistance of 315Omega/cnt for BL/N+ and 1518Omega/cnt for BL/P+ in 0.16mum contacts, as well as a crack-free integration scheme and low level of defect density.

引用

页码：282 / 284

页数：3