Key process steps for high performance and reliable 3D Sequential Integration

被引：0

作者：

Lu, C-M. V. ^{[1
,2
]}

Deprat, F. ^{[1
]}

Fenouillet-Beranger, C. ^{[1
]}

Batude, P. ^{[1
]}

Garros, X. ^{[1
]}

Tsiara, A. ^{[1
]}

Leroux, C. ^{[1
]}

Gassilloud, R. ^{[1
]}

Nouguier, D. ^{[2
]}

Ney, D. ^{[2
]}

Federspiel, X. ^{[2
]}

Besombes, P. ^{[1
]}

Toffoli, A. ^{[1
]}

Romano, G. ^{[1
,2
]}

Rambal, N. ^{[1
]}

Delaye, V. ^{[1
]}

Barge, D. ^{[2
]}

Samson, M. -P. ^{[1
,2
]}

Previtali, B. ^{[1
]}

Tabone, C. ^{[1
]}

Pasini, L. ^{[1
,2
]}

Brunet, L. ^{[1
]}

Andrieu, F. ^{[1
]}

Micoud, J. ^{[1
]}

Skotnicki, T. ^{[2
]}

Vinet, M. ^{[1
]}

机构：

[1] Univ Grenoble Alpes, CEA, LETI, MINATEC Campus,17 Rue Martyrs, Grenoble, France

[2] STMicroelectronics, Crolles, France

来源：

2017 SYMPOSIUM ON VLSI TECHNOLOGY | 2017年

关键词：

3D sequential integration; low thermal budget process flow; gate stack reliability; iBEOL ULK reliability;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500 degrees C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525 degrees C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550 degrees C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

引用

页码：T226 / T227

页数：2

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