SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors

被引：21

作者：

Yamaoka, Masanao ^{[1
]}

Tsuchiya, Ryuta ^{[1
]}

Kawahara, Takayuki ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Tokyo 1858601, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 11期

关键词：

back-gate bias; low-leakage current; operating margin; SRAM; thin buried-oxide fully depleted silicon-on-insulator (thin-BOX FD-SOI) transistor;

D O I：

10.1109/JSSC.2006.882891

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The deterioration of operating margin and increasing leakage current in SRAM are becoming critical problems with the advance of process scaling. To solve these problems, we propose a low-power SRAM circuit using thin buried-oxide fully depleted silicon-on-insulator transistors. The back-gate bias is introduced to the SRAM circuits and acquires high operating margin and highspeed operation under low supply voltage. The leakage current in stand-by state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation and 90% less stand-by power.

引用

页码：2366 / 2372

页数：7

共 7 条

[1] MATCHING PROPERTIES OF MOS-TRANSISTORS [J].

PELGROM, MJM ;

DUINMAIJER, ACJ ;

WELBERS, APG .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1433-1440

[2] STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS [J].

SEEVINCK, E ;

LIST, FJ ;

LOHSTROH, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :748-754

[3]

TSUCHIYA R, 1920, IEDM, P631

[4] Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology [J].

Yamaoka, M ;

Osada, K ;

Tsuchiya, R ;

Horiuchi, M ;

Kimura, S ;

Kawahara, T .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :288-291

[5] A 300MHz 25μA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor [J].

Yamaoka, M ;

Shinozaki, Y ;

Maeda, N ;

Shimazaki, Y ;

Kato, K ;

Shimada, S ;

Yanagisawa, K ;

Osada, K .

2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 :494-495

[6]

YAMAOKA M, 2005, ISSCC, P480

[7] SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors [J].

Yamaoka, Masanao ;

Tsuchiya, Ryuta ;

Kawahara, Takayuki .

2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2005, :109-112

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