High-performance noise-tolerant circuit techniques for CMOS dynamic logic

Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of similar to 115 ps and an energy dissipation of similar to 33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower.