Sampled analog architecture for DCT and DST

被引：0

作者：

Mal, AK ^{[1
]}

Basu, A ^{[1
]}

Dhar, AS ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched, properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

引用

页码：825 / 828

页数：4

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