Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

被引：15

作者：

Chin, Yoke King ^{[1
,2
]}

Pey, Kin-Leong ^{[1
]}

Singh, Navab ^{[2
]}

Lo, Guo-Qiang ^{[2
]}

Tan, Khing Hong ^{[1
]}

Ong, Chio-Yin ^{[1
]}

Tan, L. H. ^{[2
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

[2] ASTAR, Inst Microelect, Singapore 117685, Singapore

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 08期

关键词：

Dopant segregation (DS); gate-all-around (GAA); Schottky barrier (SB) MOSFET; silicon nanowire (SiNW); SOURCE/DRAIN; TRANSISTORS;

D O I：

10.1109/LED.2009.2022851

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we demonstrated dopant-segregated Schottky (DSS) p-MOSFET with gate-all-around silicon-nanowire (SiNW) channel of 10 nm in diameter. The DSS transistor shows improved performance as compared to a reference Schottky barrier (SB) transistor without dopant segregation. The DSS transistor shows I-ON of 319 mu A/mu m at a low gate overdrive of -0.6 V, high I-ON/I-OFF ratio (similar to 10(5)), and short-channel performance with subthreshold slope similar to 90 mV/dec down to 100-nm gate length with relatively thick (6 nm) deposited gate oxide. The DSS transistor also shows significant reduction (similar to 40 x lower) in the series resistance as compared to the SB transistor. The origin of the improved performance of the DSS is the thin dopant layer segregated at the nickel monosilicide/SiNW point contact which results in the enhanced hole injection at the source side and the suppressed electron injection at the drain side.

引用

页码：843 / 845

页数：3

共 14 条

[1] Analysis of the parasitic S/D resistance in multiple-gate FETs [J].

Dixit, A ;

Kottantharayil, A ;

Collaert, N ;

Goodwin, M ;

Jurezak, M ;

De Meyer, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (06) :1132-1140

[2]

Kinoshita A, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P158

[3]

Kinoshita A, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P168

[4] Overview and status of metal S/D Schottky-barrier MOSFET technology [J].

Larson, JM ;

Snyder, JP .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (05) :1048-1058

[5] Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors [J].

Peng, J. W. ;

Lee, S. J. ;

Liang, G. C. Albert ;

Singh, N. ;

Zhu, S. Y. ;

Lo, G. Q. ;

Kwong, D. L. .

APPLIED PHYSICS LETTERS, 2008, 93 (07)

[6] High-performance fully depleted silicon-nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices [J].

Singh, N. ;

Agarwal, A. ;

Bera, L. K. ;

Liow, T. Y. ;

Yang, R. ;

Rustagi, S. C. ;

Tung, C. H. ;

Kumar, R. ;

Lo, G. Q. ;

Balasubramanian, N. ;

Kwong, D. -L. .

IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :383-386

[7]

Singh N., 2006, IEDM, P548

[8]

Sze S.M., 2007, PHYS SEMICONDUCTOR D, P304

[9] Nickel-silicided Schottky junction CMOS transistors with gate-all-around nanowire channels [J].

Tan, E. J. ;

Pey, K. L. ;

Singh, N. ;

Lo, G. Q. ;

Chi, D. Z. ;

Chin, Y. K. ;

Tang, L. J. ;

Lee, P. S. ;

Ho, C. K. F. .

IEEE ELECTRON DEVICE LETTERS, 2008, 29 (08) :902-905

[10] Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel [J].

Tan, Eu Jin ;

Pey, Kin-Leong ;

Singh, Navab ;

Lo, Guo-Qiang ;

Chi, Dong Zhi ;

Chin, Yoke King ;

Hoe, Keat Mun ;

Cui, Guangda ;

Lee, Pooi See .

IEEE ELECTRON DEVICE LETTERS, 2008, 29 (10) :1167-1170

← 1 2 →