Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

被引：4

作者：

Marconi, S. ^{[1
,2
,3
]}

Orfanelli, S. ^{[3
]}

Karagounis, M. ^{[4
]}

Hemperek, T. ^{[5
]}

Christiansen, J. ^{[3
]}

Placidi, P. ^{[1
,2
]}

机构：

[1] Univ Perugia, Dept Engn, Via G Duranti 93, I-06125 Perugia, Italy

[2] INFN Sect Perugia, Via Pascoli, I-06123 Perugia, Italy

[3] CERN, CH-1211 Geneva, Switzerland

[4] Fachhsch Dortmund, Sonnenstr 96, D-44139 Dortmund, Germany

[5] Univ Bonn, Inst Phys, Nussallee 12, D-53115 Bonn, Germany

来源：

JOURNAL OF INSTRUMENTATION | 2017年 / 12卷

关键词：

Digital electronic circuits; Front-end electronics for detector readout; Simulation methods and programs; VLSI circuits; LHC;

D O I：

10.1088/1748-0221/12/02/C02017

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

引用

页数：9

共 11 条

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