Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?

An experimental study of the effects of gate line edge roughness (LER) on the electrical characteristics of bulk MOSFET devices was performed. Device simulation had previously predicted that gate LER causes off-state current to increase. In our experiments, gate LER was deliberately introduced in devices with 40 nm or longer physical gate length, and we found about 3X I-OFF increase (for 40 nm gate length) in the I-OFF - I-ON plot. In our devices, Source/Drain (S/D) extensions are produced by implants self-aligned to gate edges. Simulation results indicate that what really matters is the roughness induced of the S/D to channel junctions by gate LER. Implantation scattering and dopant diffusion cause the S/D to channel junctions to be smoother than the gate edges. This will partially reduce the differences in the I-OFF - I-ON curves caused by differing amounts of gate LER. By optimizing our process flows, we obtained a minimized gate LER (Edge RMS < 2 nm). We believe that the consequence of this minimized LER is secondary to the impact of other process variations across wafer for devices with 40 nm or longer gate length.