Optimization of Stress Memorization Technique for 45 nm Complementary Metal-Oxide-Semiconductor Technology

被引：2

作者：

Morifuji, Eiji ^{[1
]}

Eiho, Ayumi ^{[1
]}

Sanuki, Tomoya ^{[1
]}

Iwai, Masaaki ^{[1
]}

Matsuoka, Fumitomo ^{[1
]}

机构：

[1] Toshiba Co Ltd, Syst LSI Div, Saiwai Ku, Kawasaki, Kanagawa 2128520, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2009年 / 48卷 / 03期

关键词：

D O I：

10.1143/JJAP.48.031203

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The effect of stress memorization technique (SMT) on performance of transistors and power reduction is intensively studied. A 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously by choosing the appropriate stressor film with a large stress change by spike rapid thermal annealing (RTA). Stress distribution in the channel region for SMT is confirmed to be uniform; hence, the layout dependence is minimized and the performance is maximized in aggressively scaled complementary metal-oxide-semiconductor (CMOS) with dense gate pitch rule (190 nm) in 45 nm technology node. (C) 2009 The Japan Society of Applied Physics

引用

页数：5

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