Optimization of Stress Memorization Technique for 45 nm Complementary Metal-Oxide-Semiconductor Technology

The effect of stress memorization technique (SMT) on performance of transistors and power reduction is intensively studied. A 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously by choosing the appropriate stressor film with a large stress change by spike rapid thermal annealing (RTA). Stress distribution in the channel region for SMT is confirmed to be uniform; hence, the layout dependence is minimized and the performance is maximized in aggressively scaled complementary metal-oxide-semiconductor (CMOS) with dense gate pitch rule (190 nm) in 45 nm technology node. (C) 2009 The Japan Society of Applied Physics