Test generation for VLSI circuits from testability profile distribution

Testing a VLSI circuit is the process of verifying a circuit is functioning according to specification. The testability profile of a circuit is a statistical measure of the "ease" or "difficulty" of testing a VLSI circuit. The profile can be used to guide test generators in a preprocessing step. In this paper, we propose a new method of modeling the testability profile. The method is based on previous work. In the paper we discuss the tools used in test generation for a VLSI circuit. These tools include circuit and fault modeling, test generation algorithms, test simulation programs and testability profile algorithms. A relation between test generation and testability profile is used in the new model for testability.