An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

被引:80
作者
Johnson, Anju P. [1 ]
Chakraborty, Rajat Subhra [1 ]
Mukhopadyay, Debdeep [1 ]
机构
[1] Indian Inst Technol Kharagpur, Secured Embedded Architecture Lab, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India
关键词
Digital clock manager (DCM); dynamic partial reconfiguration (DPR); field-programmable gate arrays (FPGAs); true random number generator (TRNG);
D O I
10.1109/TCSII.2016.2566262
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
True random number generators (TRNGs) play a very important role in modern cryptographic systems. Field-programmable gate arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this brief, we present a highly efficient and tunable TRNG based on the principle of beat frequency detection, specifically for Xilinx-FPGA-based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through dynamic partial reconfiguration to improve randomness qualities. We describe the mathematical model of the TRNG operations and experimental results for the circuit implemented on a Xilinx Virtex-V FPGA. The proposed TRNG has low hardware footprint and built-in bias elimination capabilities. The random bitstreams generated from it pass all tests in the NIST statistical testsuite.
引用
收藏
页码:452 / 456
页数:5
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