Multistate Memory Enabled by Interface Engineering Based on Multilayer Tungsten Diselenide

size in the information era continuously required to miniaturize the memory devices with high data storage capability. Atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) are promising candidates for flexible and transparent electronic and optoelectronic devices with high integration density. Multistate memory devices based on TMDs could possess high data storage capability with a large integration density and thus exhibit great potential applications in the field of data storage. Here, we report the multistate data storage based on multilayer tungsten diselenide (WSe2) transistors by interface engineering. The multiple resistance states of the WSe2 transistors are achieved by applying different gate voltage pulses, and the switching ratio of the memory can be as large as 10(5) with high cycling endurance. The water and oxygen molecules (H2O/O-2) trapped at the interface between the SiO2 substrate and WSe2 introduce the trap states and thus the large hysteresis of the transfer curves, which leads to the multistate data storage. In addition, the laminated Au thin film electrodes make the contact interface between the electrodes and WSe2 free of dangling bond and Fermi level pinning, thus giving rise to the excellent performance of memory devices. Importantly, the interface trap states can be easily controlled by a simple oxygen plasma treatment of the SiO2 substrate, and subsequently, the performance of the multistate memory devices can be manipulated. Our findings provide a simple and efficient strategy to engineer the interface states for the multistate data storage applications and would motivate more investigations on the trap state-associated applications.