Optical RAM-enabled cache memory and optical routing for Chip Multiprocessors: technologies and architectures

被引：1

作者：

Pleros, Nikos ^{[1
,2
]}

Maniotis, Pavlos ^{[1
,2
]}

Alexoudi, Theoni ^{[1
,2
]}

Fitsios, Dimitris ^{[1
,2
]}

Vagionas, Christos ^{[1
,2
]}

Papaioannou, Sotiris ^{[1
,2
]}

Vyrsokinos, K. ^{[2
]}

Kanellos, George T. ^{[2
]}

机构：

[1] Aristotle Univ Thessaloniki, Dept Informat, Thessaloniki, Greece

[2] Inst Informat Technol, Ctr Res & Technol Hellas, Thessaloniki, Greece

来源：

OPTICAL INTERCONNECTS XIV | 2014年 / 8991卷

关键词：

Optical interconnects; optical routing; Optical RAM; optical memory; Silicon photonics;

D O I：

10.1117/12.2042732

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

The processor-memory performance gap, commonly referred to as "Memory Wall" problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

引用

页数：8

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