SAW-Less Analog Front-End Receivers for TDD and FDD

被引：64

作者：

Fabiano, Ivan ^{[1
]}

Sosio, Marco ^{[2
]}

Liscidini, Antonio ^{[3
]}

Castello, Rinaldo ^{[1
]}

机构：

[1] Univ Pavia, Dept Elect Engn & Comp Sci, I-27100 Pavia, Italy

[2] Marvell Italy, Analog Signal Proc Grp, I-27100 Pavia, Italy

[3] Univ Toronto, Edward S Rogers Sr Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2013年 / 48卷 / 12期

关键词：

25% duty cycle; baseband; blocker tolerant; current-mode; direct conversion; divider; dynamic range; frequency-division duplexing (FDD); GSM; harmonic mixing; linearity; low-noise transconductor amplifier (LNTA); low power; noise folding; reciprocal mixing; resonant mixer; SAW-less; time-division duplexing (TDD); UMTS; W-CDMA;

D O I：

10.1109/JSSC.2013.2271859

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multistandard SAW-less receiver is designed exploring a current-mode architecture. A class-AB common-gate transformer-based low-noise transconductor amplifier (LNTA) is used to provide high linearity and harmonic filtering. A resonant passive mixer is adopted in order to allow the current-mode operation and improve the harmonic rejection. A low-power divider with intrinsic 25% duty-cycle is introduced to drive the passive mixer. A second-order Rauch biquad with complex poles makes-up the IQ blocker tolerant baseband. The receiver is designed to be suitable for SAW-less TDD and typical FDD applications with 3.8 and 1.9 dB of NF and > 18 and > 16 dBm of IIP3, respectively, using only 32 mW for each receiver.

引用

页码：3067 / 3079

页数：13

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