SALIENT: Ultra-Fast FPGA-based Short Read Alignment

被引:0
|
作者
Khaleghi, Behnam [1 ]
Zhang, Tianqi [1 ]
Martino, Cameron [1 ]
Armstrong, George [1 ]
Akel, Ameen [2 ]
Curewitz, Ken [2 ]
Eno, Justin [2 ]
Eilert, Sean [2 ]
Knight, Rob [1 ]
Moshiri, Niema [1 ]
Rosing, Tajana [1 ]
机构
[1] Univ Calif San Diego, Comp Sci & Engn Dept, La Jolla, CA 92093 USA
[2] Micron Technol Inc, Lehi, UT USA
来源
2022 21ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2022) | 2022年
基金
美国国家科学基金会;
关键词
BOWTIE;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
State-of-the-art high-throughput DNA sequencers output terabytes of short reads that typically need to be aligned to a reference genome in order to perform downstream analyses. Because alignment typically dominates the total run time of bioinformatics pipelines, a number of recent work sought to accelerate it in hardware. However, existing FPGA implementations did not fully optimize the alignment algorithms for the FPGA hardware and mainly focused on a subset of alignment problems, e.g., ungapped alignment with a limited number of mismatches, which hinder their practical utility. In this work, we analyze the existing alignment methods and identify and leverage opportunities for FPGA acceleration. Our alignment framework, SALIENT, first carries out an ultra-fast ungapped alignment, which supports a flexible number of mismatches. Based on the underlying bioinformatics pipeline and the information provided by the ungapped aligner, SALIENT then identifies a fraction of reads that need to go through its gapped aligner, thus improving alignment throughput. We extensively evaluate SALIENT using diverse datasets. Experimental results indicate that SALIENT, running on a single Xilinx Alveo U280 device, delivers an average throughput of 546 million bases/second, outperforming the stateof-the-art minimap2 software by 40x, and Bowtie2 by up to 107x, with a similar or slightly better (similar to 0.1%-0.5%) alignment and error (false negative/positive) rate. Compared to the existing ungapped FPGA aligners [1]-[4], SALIENT has 9.4-18x higher throughput/Watt, while compared to the gapped aligners [5], [6], it is 28-35x better. SALIENT achieves 7.6x higher throughput than Illumina DRAGEN Bio-IT Platform [7].
引用
收藏
页码:205 / 214
页数:10
相关论文
共 50 条
  • [21] Fast and SNP-aware short read alignment with SALT
    Wei Quan
    Bo Liu
    Yadong Wang
    BMC Bioinformatics, 22
  • [22] Ultra-fast detection of salient contours through horizontal connections in the primary visual cortex
    Loxley, P. N.
    Bettencourt, L. M.
    Kenyon, G. T.
    EPL, 2011, 93 (06)
  • [23] FPGA-based Embedded System Implementation of Audio Signal Alignment
    Stornaiuolo, Luca
    Perini, Massimo
    Santambrogio, Marco D.
    Sciuto, Donatella
    2019 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 2019, : 132 - 139
  • [24] An FPGA-based accelerator for multiple biological sequence alignment with DIALIGN
    Boukerche, Azzedine
    Correa, Jan Mendonca
    Magalhaes Alves de Me, Alba Cristina
    Jacobi, Ricardo Pezzuol
    Rocha, Adson Ferreira
    HIGH PERFORMANCE COMPUTING - HIPC 2007, PROCEEDINGS, 2007, 4873 : 71 - +
  • [25] Exploring Sequence Alignment Algorithms on FPGA-based Heterogeneous Architectures
    Chang, Xin
    Escobar, Fernando A.
    Valderrama, Carlos
    Robert, Vincent
    PROCEEDINGS IWBBIO 2014: INTERNATIONAL WORK-CONFERENCE ON BIOINFORMATICS AND BIOMEDICAL ENGINEERING, VOLS 1 AND 2, 2014, : 330 - 341
  • [26] USE LFSRS TO BUILD FAST FPGA-BASED COUNTERS
    KLEIN, B
    ELECTRONIC DESIGN, 1994, 42 (06) : 87 - &
  • [27] FAST: An FPGA-based simulation testbed for ATM networks
    Stiliadis, D
    Varma, A
    1996 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS - CONVERGING TECHNOLOGIES FOR TOMORROW'S APPLICATIONS, VOLS. 1-3, 1996, : 374 - 378
  • [28] A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration
    Kulkarni, Amit
    Bahrebar, Poona
    Stroobandt, Dirk
    Stramondo, Giulio
    Ciobanu, Catalin Bogdan
    Varbanescu, Ana Lucia
    2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT), 2017, : 203 - 206
  • [29] An FPGA-based hardware emulator for fast fault emulation
    Hong, JH
    Hwang, SA
    Wu, CW
    PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 345 - 348
  • [30] An FPGA-based eigenfilter using fast Hebbian learning
    Lam, KP
    Mak, ST
    2003 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL II, PROCEEDINGS: SPEECH II; INDUSTRY TECHNOLOGY TRACKS; DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS; NEURAL NETWORKS FOR SIGNAL PROCESSING, 2003, : 765 - 768