Characterizing Soft Error Vulnerability of CPUs Across Compiler Optimizations and Microarchitectures

In this paper, we present a fine-grained characterization of the impact of transient faults (soft errors) on program execution for different compiler optimization levels and two out-of-order microarchitectures through extensive microarchitecture-level fault injection experiments. We evaluate how the different levels of compiler optimization impact the failure probability of the most important hardware structures in two different out-of-order Arm microarchitectures (Cortex-A15 and CortexA72). We analyze 32 different executables: sources come from eight different benchmarks with large datasets, each one compiled with three different levels of compiler optimization (O1, O2, O3) and the baseline unoptimized code level (O0); execution times of the 32 binaries range from 72M cycles to 1.4B cycles. We show how the different compiler optimization levels affect the vulnerability of eight important hardware structures. We perform extensive soft error fault injection campaigns to measure with high statistical significance the Architectural Vulnerability Factor (AVF) of all hardware structures at each optimization level, and identify the structures whose vulnerability is more sensitive to compiler optimizations. Finally, we aggregate the vulnerabilities of the hardware structures into the overall failure rates of the microprocessor and complement with a performanceaware comparison of all optimization levels. The performanceaware vulnerability analysis shows that higher optimization levels counterbalance their increased vulnerability with the speedup the deliver. From the failure rates sole point of view, an unprotected design has variable behavior, however, when typical ECC protection is employed the O2 optimization level is consistently the most robust one, while for more recent microarchitectures, O1 can be equally robust to O2 which is not the case in older microarchitectures.