Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance

被引：325

作者：

Ni, Kai ^{[1
]}

Sharma, Pankaj ^{[1
]}

Zhang, Jianchi ^{[1
]}

Jerry, Matthew ^{[1
]}

Smith, Jeffery A. ^{[1
]}

Tapily, Kandabara ^{[2
]}

Clark, Robert ^{[2
]}

Mahapatra, Souvik ^{[3
]}

Datta, Suman ^{[1
]}

机构：

[1] Univ Notre Dame, Elect Engn Dept, Notre Dame, IN 46556 USA

[2] Amer LLC, TEL Technol Ctr, Albany, NY 12203 USA

[3] Indian Inst Technol, Elect Engn Dept, Bombay 400076, Maharashtra, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2018年 / 65卷 / 06期

关键词：

Charge trapping; ferroelectric FET (FeFET); Hf0.5Zr0.5O2 (HZO); interlayer (IL); KINETICS; DEVICE; OXIDE; ZRO2;

D O I：

10.1109/TED.2018.2829122

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify VTH shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and VTH shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 degrees C and endurance up to 5 x 10(6) cycles initiated by the IL breakdown. Endurance up to 10(12) cycles of partial polarization switching is shown inmetal-FE-metal capacitor, in the absence of IL. A comprehensive metal-FE-insulator-semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.

引用

页码：2461 / 2469

页数：9

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