Shaped E-Beam lithography integration work for advanced ASIC manufacturing Progress report

被引：6

作者：

Pain, L ^{[1
]}

Charpin, M ^{[1
]}

Laplanche, Y ^{[1
]}

Henry, D ^{[1
]}

机构：

[1] CEA, LETI Grenoble, F-38054 Grenoble 9, France

来源：

EMERGING LITHOGRAPHIC TECHNOLOGIES VI, PTS 1 AND 2 | 2002年 / 4688卷

关键词：

E-Beam; lithography; photoresist;

D O I：

10.1117/12.472335

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the sub-90 nm node integrated circuits design rules, ITRS forecasts require minimal gate line width down to 55-35 nm. To reach such aggressive targets, most advanced optical lithography tools combined with all reticle enhancement techniques will be requested inducing important manufacturing cost and mask cycle time increases. In order to address prototyping market and reduce fabrication cost, shaped electron beam lithography may represent a technological alternative for cost reduction due to its high resolution and potential throughput capabilities. This paper is focused on the integration of this technology in standard ASIC plant, including resist process and overlay capabilities.

引用

页码：607 / 618

页数：4