Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems

被引:0
作者
Paolieri, Marco [1 ]
Quinones, Eduardo [1 ]
Cazorla, Francisco J. [1 ]
Bernat, Guillem
Valero, Mateo [1 ]
机构
[1] BSC, Barcelona, Spain
来源
ISCA 2009: 36TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE | 2009年
关键词
Multicore; real-time embedded systems; hard real-time; interconnection network; cache partitioning; WCET; analyzability;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent a good design solution for such systems due to their high performance, low cost and power consumption characteristics. However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when accessing shared hardware resources. In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time analizability for the hard real-time tasks so that they can meet their deadlines. Moreover our architecture proposal provides high-performance for the non hard real-time tasks.
引用
收藏
页码:57 / 68
页数:12
相关论文
共 20 条
  • [1] Akesson B., 2007, CODES ISSS
  • [2] ANDREI A, 2008, VLSID
  • [3] [Anonymous], 2005, TRIC 1 32 BIT UN PRO
  • [4] [Anonymous], RTSS
  • [5] BUI BD, 2008, IMPACT CACHE PARTITI
  • [6] Chiou Derek., 2000, DAC
  • [7] DEBOSSCHERE K, 2007, HIGH PERFORMANCE EMB
  • [8] El-Haj-Majmoud Ali, 2005, CASES
  • [9] ELHAJMAHMOUD A, 2004, CASES
  • [10] KHATIB IA, 2006, DAC