Three-Dimensional Integration Technology for Advanced Focal Planes

被引：0

作者：

Keast, Craig ^{[1
]}

Aull, Brian ^{[1
]}

Burns, Jim ^{[1
]}

Chen, Chenson ^{[1
]}

Knecht, Jeff ^{[1
]}

Tyrrell, Brian ^{[1
]}

Warner, Keith ^{[1
]}

Wheeler, Bruce ^{[1
]}

Suntharalingam, Vyshi ^{[1
]}

Wyatt, Peter ^{[1
]}

Yost, Donna ^{[1
]}

机构：

[1] MIT, Lincoln Lab, Lexington, MA 02420 USA

来源：

MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION | 2009年 / 1112卷

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

引用

页码：15 / 23

页数：9