An ultra low power 10 Gbps LVDS output driver

This paper describes a new topology and implementation of a 10 Gbps LVDS (low voltage differential signaling) voltage mode output driver designed for high speed data transfer applications. Using a positive feedback technique, the driver achieves ultra low power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized and good signal integrity is achieved. The driver, which consists of a pre-driver and an output stage, consumes a total of 15.63mW at speed power. It provides a single ended output swing of 400mV and a common mode voltage of 1.25V which are compliant with LVDS standards. In measurements, the driver, which was a part of an equalizer chip, achieved peak to peak jitter of 11psee at 10Gbps. The chip is fabricated in a standard 2.5V/1.2V SiGe BiCMOS technology with 100 GHz peak f(t), and packaged in a commercial LLP package.