Design-Oriented Analysis of Quantization-Induced Limit Cycles in a Multiple-Sampled Digitally Controlled Buck Converter

被引：19

作者：

Bradley, Mark ^{[1
]}

Alarcon, Eduard ^{[2
]}

Feely, Orla ^{[1
]}

机构：

[1] Univ Coll Dublin, Sch Elect Elect & Commun Engn, Dublin 4, Ireland

[2] Barcelona Tech UPC, Dept Elect, Barcelona 08034, Spain

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2014年 / 61卷 / 04期

关键词：

DC-DC power converters; digital control; limit cycles; nonlinear dynamics; quantization; DC-DC CONVERTER; RESOLUTION;

D O I：

10.1109/TCSI.2013.2283671

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Digital control of switching power converters is an area which has seen increased attention in recent years. However, quantization in the feedback loop from the analog-to-digital (A/D) converter and the digital pulse width modulator (DPWM) may cause limit cycle oscillations to manifest, which are generally seen as being undesirable. This paper presents an analysis of the limit cycle behavior found in a multiple-sampled digitally controlled buck converter. The limit cycles which may arise in the system are characterized and conditions to prevent these oscillations from occurring are presented.

引用

页码：1192 / 1205

页数：14

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