A Dual-loop Phase Locked Loop with Frequency to Voltage Converter

This paper proposes a 1.5-GHz ring oscillator-based dual-loop phase locked loop (PLL) with a frequency-to-voltage converter (FVC). By forming an additional high bandwidth path in the conventional PLL with the FVC, the proposed dual-loop PLL can effectively suppress the voltage controlled oscillator (VCO) noise and reference noise. Tested with an arbitrary power supply noise injection, the phase noise of the proposed PLL with FVC was -88.6 dBc/Hz at a 1-MHz offset, while that of the conventional PLL was -78.4 dBc/Hz. The measured reference spur was also reduced from -38.7 dBc to -59.3 dBc. The proposed dual-loop PLL was fabricated in a 28-nm CMOS process. It occupies an area of 0.23 mm(2) and consumes 4 mW from a 1.0-V power supply when it operates at 1.5-GHz.