A Dual-loop Phase Locked Loop with Frequency to Voltage Converter

被引:1
|
作者
Jin, Xuefan [1 ]
Kwon, Kee-Won [1 ]
Choi, Young-Shig [2 ]
Chun, Jung-Hoon [1 ]
机构
[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon, South Korea
[2] Pukyong Natl Univ, Dept Elect, Busan, South Korea
基金
新加坡国家研究基金会;
关键词
Ring oscillator; dual-loop phase locked loop; frequency to voltage converter;
D O I
10.5573/JSTS.2019.19.3.292
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a 1.5-GHz ring oscillator-based dual-loop phase locked loop (PLL) with a frequency-to-voltage converter (FVC). By forming an additional high bandwidth path in the conventional PLL with the FVC, the proposed dual-loop PLL can effectively suppress the voltage controlled oscillator (VCO) noise and reference noise. Tested with an arbitrary power supply noise injection, the phase noise of the proposed PLL with FVC was -88.6 dBc/Hz at a 1-MHz offset, while that of the conventional PLL was -78.4 dBc/Hz. The measured reference spur was also reduced from -38.7 dBc to -59.3 dBc. The proposed dual-loop PLL was fabricated in a 28-nm CMOS process. It occupies an area of 0.23 mm(2) and consumes 4 mW from a 1.0-V power supply when it operates at 1.5-GHz.
引用
收藏
页码:292 / 299
页数:8
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