Particle MCMC algorithms and architectures for accelerating inference in state-space models

被引:17
作者
Mingas, Grigorios [1 ]
Bottolo, Leonardo [2 ]
Bouganis, Christos-Savvas [1 ]
机构
[1] Imperial Coll London, Dept Elect & Elect Engn, London SW7 2AZ, England
[2] Univ Cambridge, Dept Med Genet, Cambridge CB2 OQQ, England
基金
英国惠康基金; 英国工程与自然科学研究理事会;
关键词
Markov Chain Monte Carlo; Particle filter; Field programmable gate array; Bayesian inference; Hardware acceleration; CHAIN MONTE-CARLO; MARKOV;
D O I
10.1016/j.ijar.2016.10.011
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Particle Markov Chain Monte Carlo (pMCMC) is a stochastic algorithm designed to generate samples from a probability distribution, when the density of the distribution does not admit a closed form expression. pMCMC is most commonly used to sample from the Bayesian posterior distribution in State-Space Models (SSMs), a class of probabilistic models used in numerous scientific applications. Nevertheless, this task is prohibitive when dealing with complex SSMs with massive data, due to the high computational cost of pMCMC and its poor performance when the posterior exhibits multi -modality. This paper aims to address both issues by: 1) Proposing a novel pMCMC algorithm (denoted ppMCMC), which uses multiple Markov chains (instead of the one used by pMCMC) to improve sampling efficiency for multi-modal posteriors, 2) Introducing custom, parallel hardware architectures, which are tailored for pMCMC and ppMCMC. The architectures are implemented on Field Programmable Gate Arrays (FPGAs), a type of hardware accelerator with massive parallelization capabilities. The new algorithm and the two FPGA architectures are evaluated using a large-scale case study from genetics. Results indicate that ppMCMC achieves 1.96x higher sampling efficiency than pMCMC when using sequential CPU implementations. The FPGA architecture of pMCMC is 12.1x and 10.1x faster than state-of-the-art, parallel CPU and GPU implementations of pMCMC and up to 53x more energy efficient; the FPGA architecture of ppMCMC increases these speedups to 34.9x and 41.8x respectively and is 173x more power efficient, bringing previously intractable SSM-based data analyses within reach. (C) 2016 The Authors. Published by Elsevier Inc.
引用
收藏
页码:413 / 433
页数:21
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