SVA Checker Generator for FPGA-Based Verification Platform

被引:0
作者
Mohamad, Nurita [1 ]
Ooi, Chia Yee [1 ]
Ismail, Nordinah [1 ]
Teh, Jwing [2 ]
机构
[1] Univ Teknol Malaysia, Malaysia Japan Int Inst Technol, Kuala Lumpur, Malaysia
[2] Altera Corp Technol Ctr, George Town, Malaysia
来源
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2016年
关键词
assertion; FPGA; verification; SystemVerilog;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper discusses development of FPGA-based verification platform which consists of SystemVerilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion checker produces single bit-1 which indicates an assertion fails while assertion collection modules must be simple and fast enough to collect the assertion results from assertion checker. In our work, collection module is implemented as arbiter and memory blocks. Case studies have been conducted on 8-bit counter and 8-bit FIFO with 10 assertions and 8 design bugs. Comparison has been done with assertion checker derived from MBAC approach in terms of checker's size. The comparison has showed that the checker size can be reduced further for 17.39%.
引用
收藏
页码:1750 / 1753
页数:4
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