Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications

被引:27
作者
Goel, Anubha [1 ]
Rewari, Sonam [2 ]
Verma, Seema [3 ]
Gupta, R. S. [1 ]
机构
[1] GGSIPU, Maharaja Agrasen Inst Technol, Dept Elect & Commun Engn, New Delhi, India
[2] Delhi Tech Univ, Dept Elect & Commun Engn, New Delhi, India
[3] Banasthali Vidyapith, Dept Elect, Banasthali 304022, Rajasthan, India
关键词
Nanotube; dual-metal; junctionless; analog; MOSFET; short channel effects (SCE); INDUCED DRAIN LEAKAGE; GATE; MOSFET; PERFORMANCE; INSIGHT; FET;
D O I
10.1007/s11664-020-08541-9
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Dual-metal junctionless nanotube field-effect transistors (DMJN-TFETs) for improvised analog and digital applications are described. It has been realized that, compared with existing junctionless nanowire FETs, in particular, junctionless-gate all around (J-GAA) metal oxide semiconductors (MOS) FETs, dual-metal junctionless-gate all around (DMJ-GAA) MOSFETs, and junctionless nanotube (JN) FETs, DMJN-TFET MOSFETs exhibit higher I-ds, g(m), g(d) and f(T) compared with the JNFETs, making it a favorable device for high-frequency analog FET applications. DMJN TFETs exhibit a surpassing I-ON/I-OFF ratio, with the subthreshold slope approaching the ideal values, a mitigated device channel resistance (R-ch), advanced early voltage (V-EA), a higher transconductance generation factor, maximum transducer power gain, unilateral power gain, and minimized noise conductivity and noise figure. Also, the small signal metrics including the transmission coefficients (S-21 and S-12) and reflection coefficients (S-11 and S-22) have been investigated to authenticate the small signal conduct of our device. These improvised characteristics make a DMJN-TFET the most suitable device design for both digital and analog applications employing FETs.
引用
收藏
页码:108 / 119
页数:12
相关论文
共 41 条
[1]  
[Anonymous], 1997, NAT TECHN ROADM SEM
[2]  
[Anonymous], 2016, ATLAS 3D DEV SIM
[3]  
Bangsaruntip S, 2009, IEDM, V12, P297
[4]   Analytic compact model of ballistic and quasi-ballistic transport for cylindrical gate-all-around MOSFET including drain-induced barrier lowering effect [J].
Cheng, He ;
Uno, Shigeyasu ;
Nakazato, Kazuo .
JOURNAL OF COMPUTATIONAL ELECTRONICS, 2015, 14 (01) :321-328
[5]  
Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
[6]   The silicon MOSFET from a transmission viewpoint [J].
Datta, S ;
Assad, F ;
Lundstrom, MS .
SUPERLATTICES AND MICROSTRUCTURES, 1998, 23 (3-4) :771-780
[7]   High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications [J].
Fahad, Hossain M. ;
Hussain, Muhammad M. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (03) :1034-1039
[8]   Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors? [J].
Fahad, Hossain M. ;
Hussain, Muhammad M. .
SCIENTIFIC REPORTS, 2012, 2
[9]   Silicon Nanotube Field Effect Transistor with Core-Shell Gate Stacks for Enhanced High-Performance Operation and Area Scaling Benefits [J].
Fahad, Hossain M. ;
Smith, Casey E. ;
Rojas, Jhonathan P. ;
Hussain, Muhammad M. .
NANO LETTERS, 2011, 11 (10) :4393-4399
[10]   Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors [J].
Fan, Jiewen ;
Li, Ming ;
Xu, Xiaoyan ;
Yang, Yuancheng ;
Xuan, Haoran ;
Huang, Ru .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (01) :213-219