Gate Length Scaling and High Drive Currents Enabled for High Performance SOI Technology using High-κ/Metal Gate

被引:0
作者
Henson, K. [1 ]
Bu, H. [1 ]
Na, M. H. [1 ]
Liang, Y. [1 ]
Kwon, U. [1 ]
Krishnan, S. [1 ]
Schaeffer, J. [2 ]
Jha, R. [1 ]
Moumen, N. [1 ]
Carter, R. [3 ]
Dewan, C. [1 ]
Donaton, R. [1 ]
Guo, D. [1 ]
Hargrove, M. [3 ]
He, W. [1 ]
Mo, R. [1 ]
Ramachandran, R. [1 ]
Ramani, K. [3 ]
Schonenberg, K. [1 ]
Tsang, Y. [3 ]
Wang, X. [1 ]
Gribelyuk, M. [1 ]
Yan, W. [1 ]
Shepard, J. [1 ]
Cartier, E. [4 ]
Frank, M. [4 ]
Harley, E. [1 ]
Arndt, R. [1 ]
Knarr, R. [1 ]
Bailey, T. [1 ]
Zhang, B. [1 ]
Wong, K. [1 ]
Graves-Abe, T. [1 ]
Luckowski, E. [2 ]
Park, D-G. [4 ]
Narayanan, V. [4 ]
Chudzik, M. [1 ]
Khare, M. [1 ]
机构
[1] IBM Corp, SRDC, Hopewell Jct, NY 12533 USA
[2] Freescale Semicond, Hopewell Jct, NY 12533 USA
[3] Adv Micro Devices Inc, Hopewell Jct, NY 12533 USA
[4] Thomas J Watson Res Ctr, Div Res, Yorktown Hts, NY 10598 USA
来源
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST | 2008年
关键词
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630 mu A/mu m and 1190 mu A/mu m have been demonstrated in 45nm groundrules at IV and 200nA/mu m off current for nFETs and pFETs, at a Tinv of 14 angstrom and 15 angstrom respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinv's down to 12 angstrom and 10.5 angstrom demonstrating the scalability of this approach for 32nm and beyond.
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页码:645 / +
页数:2
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