An Efficient Sparse CNNs Accelerator on FPGA

Convolutional Neural Networks (CNNs) have achieved remarkable performance at a huge computational cost. By improving the model sparsity, it can effectively reduce the complexity. However, with deepening of sparsity, the problems of unbalanced workloads, computing fragmentation and mapping access conflict caused by irregular sparsity have become more and more remarkable. These problems pose great challenges for efficient computation of sparse CNNs. In order to make full use of two side of sparsity introduced by activations and weights, and overcome the above problems, this paper proposes an efficient sparse CNNs accelerator on FPGA to achieve the inference acceleration. We designed and implemented the accelerator on the Zynq UltraScale+ MPSoC ZCU102 evaluation board. By running AlexNet, VGG16 and ResNet50 networks on the accelerator to evaluated the peeformance. Experimental results show that the method proposed in this paper can achieve more than 97% reduction in collision rate and 2.35x improvement in computing performance and 9.37x improvement in energy efficiency.