BSIM6: Analog and RF Compact Model for Bulk MOSFET

被引：93

作者：

Chauhan, Yogesh Singh ^{[1
]}

Venugopalan, Sriramkumar ^{[2
]}

Chalkiadaki, Maria-Anna ^{[3
]}

Ul Karim, Muhammed Ahosan ^{[2
]}

Agarwal, Harshit ^{[1
]}

Khandelwal, Sourabh ^{[2
]}

Paydavosi, Navid ^{[2
]}

Duarte, Juan Pablo ^{[2
]}

Enz, Christian C. ^{[3
]}

Niknejad, Ali M. ^{[2
]}

Hu, Chenming ^{[2
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India

[2] Univ Calif Berkeley, Berkeley, CA 94720 USA

[3] Ecole Polytech Fed Lausanne, Lausanne, Switzerland

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2014年 / 61卷 / 02期

基金：

瑞士国家科学基金会;

关键词：

Analog; BSIM4; BSIM6; compact model; RF; CIRCUIT; VOLTAGE; LAYER;

D O I：

10.1109/TED.2013.2283084

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

引用

页码：234 / 244

页数：11

共 32 条

[1]

Agarwal H., 2013, P IEEE INT C SIM SEM

[2]

[Anonymous], 2012, BSIM4 TECHNICAL MANU

[3]

[Anonymous], 2010, OPERATION MODELING M

[4]

[Anonymous], 2013, BSIM6 TECHNICAL MANU

[5] An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs [J].

Bazigos, Antonios ;

Bucher, Matthias ;

Assenmacher, Joachim ;

Decker, Stefan ;

Grabinski, Wladyslaw ;

Papananos, Yannis .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (11) :3751-3758

[6]

Chan T. Y., 1987, 1987 International Electron Devices Meeting, IEDM. Technical Digeset (Cat. No.87CH2515-5), P718, DOI 10.1109/IEDM.1987.191531

[7]

Chauhan YS, 2012, NANOTECHNOLOGY 2012, VOL 2: ELECTRONICS, DEVICES, FABRICATION, MEMS, FLUIDICS AND COMPUTATIONAL, P724

[8]

Chauhan Y. S., 2013, P IEEE 21 INT C MIX

[9]

Chauhan Y. S., 2012, P EUR SOL STAT CIRC, P30

[10] EFFECTS OF SPACE-CHARGE LAYER WIDENING IN JUNCTION TRANSISTORS [J].

EARLY, JM .

PROCEEDINGS OF THE INSTITUTE OF RADIO ENGINEERS, 1952, 40 (11) :1401-1406

← 1 2 3 4 →