GRMIN2: A heuristic simplification algorithm for generalised Reed-Muller expressions

被引:11
作者
Debnath, D
Sasao, T
机构
[1] Department of Computer Science and Electronics, Kyushu Institute of Technology
来源
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 1996年 / 143卷 / 06期
关键词
AND-EXOR; easily testable networks; logic minimisation; Reed-Muller expression;
D O I
10.1049/ip-cdt:19960826
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A generalised Reed-Muller expression (GRM) is a class of AND-EXOR expression. In a GRM, each variable may appear both complemented and uncomplemented. Networks realised using GRMs are easily tested. The paper presents GRMIN2, a heuristic simplification algorithm for GRMs of multiple-output functions. GRMIN2 uses eight rules, and as the primary objective, it reduces the number of products, and as the secondary objective, it reduces the number of literals. GRMIN2 obtains a lower bound on the number of products in GRMs and often proves the minimality of the solutions. Experimental results show that in most cases GRMs require fewer products than conventional sum-of-products expressions. GRMIN2 outperforms existing algorithms and for many functions it proved the minimalities of the solutions.
引用
收藏
页码:376 / 384
页数:9
相关论文
共 26 条
[1]   MINIMIZATION OF AND EXOR EXPRESSIONS USING REWRITE RULES [J].
BRAND, D ;
SASAO, T .
IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (05) :568-576
[2]  
COHN M, 1962, IRE T ELECT COMPUTER, V11, P284
[3]   CANONICAL RESTRICTED MIXED-POLARITY EXCLUSIVE-OR SUMS OF PRODUCTS AND THE EFFICIENT ALGORITHM FOR THEIR MINIMIZATION [J].
CSANKY, L ;
PERKOWSKI, MA ;
SCHAFER, I .
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1993, 140 (01) :69-77
[4]  
DAVIO M, 1978, DISCRETE SWITCHING F
[5]  
Debnath D., 1995, Proceedings of the ASP-DAC'95/CHDL'95/VLSI'95. Asia and South Pacific Design Automation Conference. IFIP International Conference on Computer Hardware Description Languages and their Applications. IFIP Interntional Conference on Very Large Scale Integration (IEEE Cat. No.95TH8102), P341, DOI 10.1109/ASPDAC.1995.486243
[6]  
DEBNATH D, 1995, P IFIP WG 10 5 WORKS, P257
[7]   ON MINIMAL MODULO 2 SUMS OF PRODUCTS FOR SWITCHING FUNCTIONS [J].
EVEN, S ;
KOHAVI, I ;
PAZ, A .
IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (05) :671-&
[8]  
Fujiwara H., 1985, LOGIC TESTING DESIGN
[9]  
Green D. H., 1986, MODERN LOGIC DESIGN
[10]   FAMILIES OF REED-MULLER CANONICAL-FORMS [J].
GREEN, DH .
INTERNATIONAL JOURNAL OF ELECTRONICS, 1991, 70 (02) :259-280