Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout

被引：4

作者：

Anju, Eisuke ^{[1
]}

Muneta, Iriya ^{[1
]}

Kakushima, Kuniyuki ^{[1
]}

Tsutsui, Kazuo ^{[2
]}

Wakabayashi, Hitoshi ^{[1
]}

机构：

[1] Tokyo Inst Technol, Sch Engn, Yokohama, Kanagawa 2268502, Japan

[2] Tokyo Inst Technol, Inst Innovat Res, Yokohama, Kanagawa 2268502, Japan

来源：

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2018年 / 6卷 / 01期

关键词：

Vertically-stacked nanowire FETs; accumulation mode operation; self-heating-effect; source/drain recessed contact; p/n-stacked nanowire on bulk-FinFET; 3-dimensinal 6T-SRAM layout; THERMAL CONDUCTION; SOI; TRANSPORT; BULK; SI;

D O I：

10.1109/JEDS.2018.2882406

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure. This is attributed to an increase in heat dissipation mainly from heat source to bulk wafer. Moreover, we proposed the p/n-stacked nanowire on bulk FinFET and its 6T-SRAM layout. Area of the proposed SRAM was reduced approximately 15%, as compared to the conventional cell layout.

引用

页码：1239 / 1245

页数：7

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