Modeling and Optimization of Multiground TSVs for Signals Shield in 3-D ICs

被引:37
作者
Qu, Chenbing [1 ,2 ,3 ]
Ding, Ruixue [1 ,3 ,4 ]
Liu, Xiaoxian [1 ,5 ]
Zhu, Zhangming [1 ,4 ,6 ]
机构
[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
[2] North Univ China, Taiyuan, Peoples R China
[3] Xidian Univ, Microelect & Solid State Elect, Xian 710071, Peoples R China
[4] Xidian Univ, Sch MicroElect, Xian, Peoples R China
[5] Shaanxi Univ Sci & Technol, Elect Sci & Technol, Shaanxi, Peoples R China
[6] Xidian Univ, Microelect, Xian, Peoples R China
基金
中国国家自然科学基金;
关键词
Coupling capacitance; crosstalk suppression; modeling; three-dimensional integrated circuits (3-D ICs); through-silicon via (TSV); THROUGH-SILICON-VIAS;
D O I
10.1109/TEMC.2016.2608981
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an effective loop impedance extraction method and a model of a signal through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the effective coupling substrate capacitances of multiground TSVs with different numbers and placements are calculated. Based on the calculated values of the resistance-inductance-capacitance-conductance (RLCG) parameters, the equivalent circuit and a two-port network model are established. The S-parameters of the model are validated by the simulated and measured results. Then, the effect of different patterns of ground TSVs on the central signal and coupling capacitance are discussed. Note that the hexagon pattern proposed in this paper can save the occupied area prominently without damaging the signal integrity. © 2016 IEEE.
引用
收藏
页码:461 / 467
页数:7
相关论文
共 27 条
  • [21] Prakash, 2015, P 10 INT C DES TECHN, P1, DOI DOI 10.1109/DTIS.2015.7127343
  • [22] Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs
    Song, Taigon
    Liu, Chang
    Peng, Yarui
    Lim, Sung Kyu
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (05) : 1636 - 1648
  • [23] Capacitance Expressions and Electrical Characterization of Tapered Through-Silicon Vias for 3-D ICs
    Su, Jinrong
    Wang, Fang
    Zhang, Wenmei
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2015, 5 (10): : 1488 - 1496
  • [24] Vaisband B., IEEE T CIRCUITS-II, DOI [10.1109/TC-SII.2016.2551552, DOI 10.1109/TC-SII.2016.2551552]
  • [25] Weerasekera R., 2009, 3D System Integration, P1
  • [26] Modeling and Application of Multi-Port TSV Networks in 3-D IC
    Yao, Wei
    Pan, Siming
    Achkir, Brice
    Fan, Jun
    He, Lei
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (04) : 487 - 496
  • [27] Young B., 2001, Digital signal integrity: modeling and simulation with interconects and packages