Modular PUF Coding Chain with High-Speed Reed-Muller Decoder

被引：0

作者：

Mandry, Holger ^{[1
]}

Herkle, Andreas ^{[1
]}

Kuerzinger, Ludwig ^{[3
]}

Mueelich, Sven ^{[2
]}

Becker, Joachim ^{[1
]}

Fischer, Robert F. H. ^{[2
]}

Ortmanns, Maurits ^{[1
]}

机构：

[1] Ulm Univ, Inst Microelect, Albert Einstein Allee 43, Ulm, Germany

[2] Ulm Univ, Inst Commun Engn, Albert Einstein Allee 43, Ulm, Germany

[3] Tech Univ Munich, Inst Human Machine Commun, Munich, Germany

来源：

2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2019年

基金：

美国国家科学基金会;

关键词：

Physical Unclonable Function (PUF); FPGA; generalized concatenated codes; Reed-Muller;

D O I：

10.1109/iscas.2019.8702484

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Physical Unclonable Functions (PUFs) offer the possibility to produce unique fingerprints for integrated circuits. As raw PUF responses are affected by noise, some post-processing steps are necessary. We present a coding chain test framework for PUFs on Field Programmable Gate Arrays. The framework allows easy exchange, evaluation and comparison of different PUF implementations, coding algorithms and other chain modules. For a testing framework, the execution time of the evaluated algorithm is a bottleneck, since a huge amount of runs are supposed to be done. Hence, we additionally present a new type of Reed-Muller decoder hardware architecture using parallel modules to speed up the decoding process. The decoding time could be decreased by 95% in comparison to existing implementations at the cost of 41 times higher slice count.

引用

页数：5

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