Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

被引：0
作者：
Enomoto, Tadayoshi [1 ]
Kobayashi, Nobuaki [1 ]
机构：
[1] Chuo Univ, Tokyo 1128551, Japan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 04期
关键词：
clocks; CMOS digital circuits; power consumption; SPICE; DIVISION;
D O I：
10.1587/transele.E92.C.409
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (P-AT) and leakage power (P-ST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The P-AT of the new SR circuit at a clock frequency (f(c)) of 490 MHz and a Supply voltage (V-DD) of 0.75 V was 104.1 mu W, i.e., 21.6% that (482.3 mu W) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1, 153 nW) of the conventional SR circuit.
引用
收藏
页码：409 / 416
页数：8
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