Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (P-AT) and leakage power (P-ST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The P-AT of the new SR circuit at a clock frequency (f(c)) of 490 MHz and a Supply voltage (V-DD) of 0.75 V was 104.1 mu W, i.e., 21.6% that (482.3 mu W) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1, 153 nW) of the conventional SR circuit.