A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

被引：9
|
作者：
Tien, Che-Wei [1 ,2 ]
Liu, Shen-Iuan [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 06期
关键词：
Phase-locked loop; background; minimization; supply noise; frequency subtractor; supply voltage sensitivity; RING OSCILLATOR; PLL;
D O I：
10.1109/TCSI.2017.2769721
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm(2) where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes 840 mu W. The output frequency of the DPLL is 5 GHz with a divider ratio of 64. The minimum measured supply voltage sensitivity is -0.0044[%-f(VCO)/%-V-DD]. With a 50-mV(PP), 100-kHz sinusoidal supply noise, the peak-to-peak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps.
引用
收藏
页码：1830 / 1839
页数：10
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