A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

被引：9

作者：

Tien, Che-Wei ^{[1
,2
]}

Liu, Shen-Iuan ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 06期

关键词：

Phase-locked loop; background; minimization; supply noise; frequency subtractor; supply voltage sensitivity; RING OSCILLATOR; PLL;

D O I：

10.1109/TCSI.2017.2769721

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm(2) where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes 840 mu W. The output frequency of the DPLL is 5 GHz with a divider ratio of 64. The minimum measured supply voltage sensitivity is -0.0044[%-f(VCO)/%-V-DD]. With a 50-mV(PP), 100-kHz sinusoidal supply noise, the peak-to-peak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps.

引用

页码：1830 / 1839

页数：10

共 50 条

[1] A Digital Phase-Locked Loop With Background Supply Noise Cancellation
Tseng, Yen-Min
Yen, Yu-Chi
Liu, Shen-Iuan
2021 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2021,
[2] A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation
Yeh, Che-Wei
Hsieh, Cheng-En
Liu, Shen-Iuan
2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 332 - U463
[3] DIGITAL PHASE-LOCKED LOOP SYSTEM OF RESONANCE VOLTAGE INVERTER
Zubkov I.S.
Hutsaliuk V.Y.
Yurchenko O.M.
Technical Electrodynamics, 2022, 2022 (02): : 27 - 34
[4] Overhead Minimization Techniques for Digital Phase-Locked Loop Frequency Synthesizer
Chen, Mike Shuo-Wei
2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2012, : 682 - 685
[5] A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression
Kao, Shih-Yuan
Liu, Shen-Iuan
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (04) : 592 - 602
[6] DIGITAL PHASE-LOCKED LOOP.
Furtney Jr., R.W.
1884, (17):
[7] DYNAMICS OF DIGITAL PHASE-LOCKED LOOP
MAKSAKOV, VP
RADIOTEKHNIKA I ELEKTRONIKA, 1988, 33 (05): : 999 - 1007
[8] DIGITAL PHASE-LOCKED LOOP MODELS
BELYKH, VN
RADIOTEKHNIKA I ELEKTRONIKA, 1979, 24 (11): : 2244 - 2253
[9] An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
Namgoong, Won
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (03) : 1025 - 1035
[10] JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP
YAMASHITA, M
TSUJI, T
NISHIMURA, T
MURATA, M
NAMEKAWA, T
PROCEEDINGS OF THE IEEE, 1976, 64 (11) : 1640 - 1641

← 1 2 3 4 5 →