Implementation of Improved Energy-Efficient FIR Filter Using Reversible Logic

被引：2

作者：

Sahu, Lavisha ^{[1
]}

Kumar, Umesh ^{[2
]}

Singh, Lajwanti ^{[3
]}

机构：

[1] Govt Women Engn Coll, Dept Comp Sci & Engn, Ajmer, India

[2] Govt Women Engn Coll, Dept Informat Technol & Engn, Ajmer, India

[3] Banasthali Vidyapith, Dept Elect & Commun Engn, Newai, Tonk, India

来源：

DATA SCIENCE AND BIG DATA ANALYTICS | 2019年 / 16卷

关键词：

Reversible logic; FIR; CNOT; HNG; PERES gates; Low power; Multiplier;

D O I：

10.1007/978-981-10-7641-1_19

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

The demand for high-speed processing has been increasing as a result of expanding computer and signal processing applications. Nowadays reducing the time delay and power consumption main factor of the circuit. One of the main advantage of reversible logic gates is to reduce the heat dissipation and improve the performance of circuit. Reversible logic gate is used for building complex circuits like multiplier, adder, FIR, and much more and reduce heat dissipation. FIR (finite impulse response) filter is used in various range of digital signal processing applications. This paper describes reversible Vedic FIR filter and compared with irreversible Vedic FIR filter.

引用

页码：229 / 238

页数：10

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