A Precise ΔΣ-based Digitally Controlled Oscillator (DCO) for All-Digital PLL

A Digitally Controlled Oscillator (DCO) for the frequency band of 1700-1900 MHz is presented. This architecture achieves a frequency resolution less than 1-kHz. The DCO is a part of an All-Digital Phase-Locked Loop (ADPLL) for GSM-1800 and GSM-900 applications implemented in a 0.18 mu m CMOS process. In this architecture an 18-bit delta sigma digital to analog converter and a voltage controlled LC oscillator is used. The used Delta Sigma DAC is a fourth order structure with 450 MHz sampling frequency, Over Sampling Ratio (OSR) = 128 and 118 dB SNR. The bandwidth of this Delta Sigma DAC is about 1.8 MHz. The phase noise of the presented DCO at 500 kHz offset frequency is -115 dBc/Hz.