Process/physics-based threshold voltage model for nano-scaled double-gate devices

被引：20
作者：
Kim, K [1 ]
Fossum, JG
Chuang, CT
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 2004年 / 91卷 / 03期
关键词：
D O I：
10.1080/00207210410001675653
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Compact physics/process-based model for threshold voltage in double-gate devices is presented. Predominant short-channel effects for double-gate devices, which are drain-induced barrier lowering (DIBL) and short-channel-induced barrier lowering (SCIBL), are physically analysed and modeled to be applicable to SPICE-compatible circuit simulators. The short-channel models are also developed for bulk-Si device and compared to those of double-gate devices. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled L-eff = 25 nm double-gate devices and bulk-Si device.
引用
收藏
页码：139 / 148
页数：10
相关论文
共 13 条
[1]  
CHEN Q, 2002, IEEE SOI C, P30
[2]  
CHIANG MH, 2001, P 10 INT S SOI TECHN, P421
[3]   Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current [J].
Fossum, JG ;
Kim, K ;
Chong, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (11) :2195-2200
[4]  
Frank D. J., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P553, DOI 10.1109/IEDM.1992.307422
[5]   Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs [J].
Ge, LX ;
Fossum, JG .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (02) :287-294
[6]  
KIM I, 2001, IEEE T ELECTRON DEV, V49, P295
[7]  
Semiconductor Industry Association, 2001, INT TECHN ROADM SEM
[8]   ULTRAFAST OPERATION OF 5TH-ADJUSTED P(+)-N(+) DOUBLE-GATE SOI MOSFETS [J].
TANAKA, T ;
SUZUKI, K ;
HORIE, H ;
SUGII, T .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (10) :386-388
[9]  
*TAUR MEDICI, 2003, IND STAND SIM TOOL 2
[10]   Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs [J].
Taur, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (12) :2861-2869
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